FPGA-based imprecise signed multiplier designs for high-performance image processing applications

Smarter Math for Sharper Pictures

Every digital photo you take depends on billions of tiny calculations happening in the background. Many of these calculations are multiplications, and doing them quickly and efficiently is vital for cameras, phones, and embedded devices. This paper explores how we can deliberately allow tiny, controlled errors in these multiplications to save energy and hardware, while still producing images that look virtually identical to the human eye.

Why Imperfect Can Be Good Enough

Not every computation must be perfect to be useful. In image and signal processing, the final result is viewed by people, who usually cannot see the effect of very small numerical errors. This idea, called approximate computing, trades a bit of mathematical precision for big gains in speed, power savings, and reduced chip area. Multiplication is one of the most expensive operations in such systems, and traditional designs aim for exact results with high hardware costs. The authors focus on building multipliers that handle both positive and negative numbers (signed multipliers) and are tailored for a popular reprogrammable chip platform known as FPGAs. Existing approximate multipliers were mostly designed for custom chips and for unsigned numbers, so they do not translate well to real-world image systems that rely heavily on signed arithmetic.

Building Blocks Inside a Reprogrammable Chip

Modern FPGAs are made from repeated units called lookup tables and fast carry chains that are especially good at performing additions. The authors first analyze how an exact 8-bit signed multiplier can be assembled from these blocks. They carefully examine the internal pattern of operations to spot repeated or unnecessary structures, such as duplicate logic and overly generous extensions of sign bits. By reorganizing the design, merging similar parts, and discarding product bits that are never needed due to the limited input range, they create a lean “exact” baseline multiplier that already uses fewer logic gates and shorter paths for signals to travel through the chip. This optimized baseline then serves as the foundation for their approximate designs.

Two Flavors of Approximate Multipliers

From this optimized baseline, the authors introduce two approximate 8-bit signed multipliers. Both rely on a simple idea: the least significant bits of the output contribute the least to image quality, so they can be simplified or fixed without noticeable visual impact. In Approximate Design 1, the seven least significant output bits are not computed exactly, but their internal carry signals are still generated and managed carefully. A search over many possibilities selects constant values for these low bits that keep the average error low. Approximate Design 2 goes further: it removes both the low output bits and their local carries, greatly cutting the amount of hardware. In both cases, the structure is then reshaped to pack multiple small operations into each lookup table and align them with the fast carry chains, resulting in compact circuit “netlists” that map efficiently onto the FPGA fabric.

Performance, Energy, and Image Quality

The two designs are thoroughly tested on a Xilinx Virtex-7 FPGA and compared against many existing approximate multipliers. The authors measure how many lookup tables are used, how long the slowest signal path is, and how much dynamic power the designs consume. They also exhaustively simulate all input combinations to quantify the average and worst-case multiplication error. Both new multipliers achieve a better balance of these factors than competing approaches: they use fewer resources, have shorter delays, and consume less power for similar or even smaller average errors. The coarser design, Approximate Design 2, uses the least hardware and energy, at the cost of larger worst-case error, while Approximate Design 1 offers tighter error bounds with slightly higher resource use. To demonstrate real-world impact, the authors plug these multipliers into two common image-processing tasks—image blending and smoothing—and evaluate the output with standard measures of visual quality. In both tasks, the resulting images remain very close to those produced by an exact multiplier, with high peak signal-to-noise ratios and structural similarity scores, and no obvious degradation to human observers.

What This Means for Everyday Devices

The work shows that carefully designed “good enough” arithmetic can significantly reduce the size and energy use of reprogrammable hardware while preserving image quality. By exploiting the natural tolerance of images to small numerical errors and by tailoring the design to the specific building blocks of FPGAs, the authors create signed multipliers that are both fast and frugal. For future cameras, embedded vision systems, or AI accelerators that must run within tight power and cost budgets, such approximate multipliers offer a practical way to squeeze out more performance without sacrificing what ultimately matters most: how the final picture looks to the human eye.

Citation: Hassan, J., Khurshid, B., Banday, S.A. et al. FPGA-based imprecise signed multiplier designs for high-performance image processing applications. Sci Rep 16, 10084 (2026). https://doi.org/10.1038/s41598-026-40524-4

Keywords: approximate computing, FPGA multipliers, image processing hardware, low power design, signed arithmetic