HiAER-spike software-hardware reconfigurable platform for event-driven neuromorphic computing at scale

Why a New Kind of Computer Matters

Most of today’s artificial intelligence runs on hardware designed decades ago for spreadsheets and word processors, not brains. As researchers push toward smarter, more efficient machines, they are bumping into limits of power, speed, and scale. This paper introduces HiAER-Spike, a neuromorphic computing platform that processes information in spikes—brief electrical events—much like real neurons do. Built as a shared resource at the San Diego Supercomputer Center, it aims to let scientists around the world experiment with brain‑inspired AI at a scale approaching small animal brains, while using far less energy than conventional systems.

Building a Brain‑Inspired Machine

HiAER-Spike is a large cluster of server machines, each packed with powerful reconfigurable chips called FPGAs. Instead of running ordinary software instructions, these chips are configured to act like vast webs of artificial neurons and synapses, called spiking neural networks. The full system is designed to handle up to about 160 million model neurons and 40 billion synapses—more than twice the number of neurons in a mouse brain—while simulating them faster than real time. A special communication scheme, called hierarchical address‑event routing, ensures that spikes can travel quickly between neuron groups on the same chip, across different chips, and even across servers, balancing dense local traffic with sparse long‑range connections, much like gray and white matter in the brain.

Fitting Huge Networks into Limited Hardware

One major challenge in building such systems is simply storing all the connections. Modern neural networks are often very large but also sparse: most possible connections are not used. HiAER-Spike takes advantage of this sparseness by storing only the existing connections in an efficient list, rather than in a full grid of all possibilities. Synaptic weights live in high‑bandwidth memory on each FPGA, while the rapidly changing states of neurons and axons are kept in faster on‑chip memory. When spikes occur, the system first looks up which synapses are affected, then fetches their strengths and updates the target neurons. This two‑step process, combined with careful packing of data in memory, keeps energy use and delay low, even as networks grow large.

Making Advanced Hardware Easy to Use

To open this specialized machine to non‑experts, the authors created a high‑level software interface in Python and C++. Users describe their spiking networks with simple objects—defining neuron types, inputs, connections, and outputs—without worrying about low‑level hardware details. The same code can run either as a local software simulation or, if submitted through the Neuroscience Gateway portal, on the HiAER-Spike hardware itself. The platform currently supports simple binary neurons and leaky integrate‑and‑fire neurons, with options for randomness in their behavior, and allows mixing different neuron types within one network. This design lets researchers prototype models on a laptop, then seamlessly scale them up to the large neuromorphic cluster.

Putting Spikes to Work on Real Tasks

To show what the platform can do, the team converted a variety of standard vision and control models into spiking form and ran them on a single core of one FPGA. They tested digit recognition on the classic MNIST dataset, gesture recognition using event‑based cameras that emit spikes instead of frames, object recognition on CIFAR‑10 images, and even control of the Atari game Pong using a spike‑based representation of motion. Across these tasks, the hardware closely matched the accuracy of software simulations after weight quantization, often differing by less than a couple of percentage points, while delivering very low latency and energy use. For example, some digit‑recognition networks reached over 98 percent accuracy with only microjoules of energy and microseconds of delay per image.

Where This New Platform Could Lead

To a lay reader, the key message is that HiAER-Spike is a flexible, brain‑inspired computing testbed that anyone in the research community can use remotely. Even in its early stage, a single core can run sizable spiking networks for tasks like recognizing gestures from event‑based cameras, using far less energy and time than many competing systems. As more cores and boards come online, and as the software adds richer neuron models and learning rules, this platform could help bridge neuroscience and AI—supporting experiments that explore how large networks of spikes can power efficient perception, decision‑making, and future low‑power intelligent devices.

Citation: Frank, G., Hota, G., Wang, K. et al. HiAER-spike software-hardware reconfigurable platform for event-driven neuromorphic computing at scale. npj Unconv. Comput. 3, 22 (2026). https://doi.org/10.1038/s44335-026-00062-8

Keywords: neuromorphic computing, spiking neural networks, FPGA accelerator, event-based vision, brain-inspired hardware