Impact of material and structural parameters on the performance of advanced low-power CNTFET-based SRAM designs

Why Faster, Cooler Memory Matters

Every tap on a smartphone screen, every AI-powered translation, and every connected medical sensor depends on tiny memory cells that quickly store and retrieve bits of information. As these gadgets shrink and workloads grow, today’s silicon-based memory circuits struggle with heat, energy waste, and reliability. This paper explores a promising alternative: using carbon nanotubes—cylinders of carbon thousands of times thinner than a human hair—to build faster, lower-power memory cells, and shows how fine-tuning their size and surrounding materials can dramatically boost performance.

Tiny Tubes Inside Tomorrow’s Chips

Conventional memory chips rely on silicon transistors that start to leak current and misbehave as engineers push them below a few dozen nanometers in size. Carbon nanotube field-effect transistors (CNTFETs) offer a different path. Their channels are built from carbon nanotubes, which can carry electrical charges with very little resistance and withstand high temperatures. The authors focus on static random-access memory (SRAM), the type of fast memory used inside processors and in many embedded devices, from smartphones to satellite sensors and Internet of Things (IoT) nodes. They compare several popular SRAM cell layouts—known as 6T, 8T, 10T, and a modified 10T design—when those cells are built using CNTFETs instead of traditional silicon devices.

Shaping Performance with Tube Size and Insulating Layers

A key knob in these designs is the diameter of the carbon nanotube itself. When the tube is narrow, the gap between energy levels in the material is large, which slows charge motion and increases delay. As the tube diameter grows, that energy gap shrinks and charges move more freely, cutting the time it takes a memory cell to switch between 0 and 1. Through detailed simulations at the 32-nanometer technology node, the authors show that increasing the nanotube diameter can reduce both write and read delays in an 8-transistor (8T) SRAM cell by roughly a quarter, making the cell far quicker to operate. However, there is a trade-off: very large tubes allow more unwanted leakage current, which can raise power consumption if pushed too far.

Smart Choices of Materials Around the Tube

Performance is also strongly shaped by the insulating material that separates the gate—a control electrode—from the nanotube channel. This material is characterized by its “dielectric constant,” a measure of how well it can store electric charge. Using materials with higher dielectric constants, such as hafnium or zirconium-based oxides instead of standard silicon dioxide, strengthens the gate’s control over the channel without physically squeezing the structure. In the simulations, raising the dielectric constant while holding the tube diameter fixed leads to noticeable reductions in both write and read delays, with only a small increase in power usage. Overall, the combined effect is an 11% drop in the power–delay product, a common figure of merit that captures how much energy is spent per switching event.

Redesigning the Memory Cell for Speed and Stability

Beyond material tuning, the circuit layout of the memory cell itself has a strong impact on behavior. The classic 6T cell uses the fewest transistors and thus tends to consume the least power, but it is more vulnerable to errors during reading and writing. Adding extra transistors in 8T and 10T designs separates the act of storing a bit from the act of accessing it, improving stability under noise and variations. The modified 10T CNTFET cell studied here goes further by providing dedicated paths for reading and writing, which sharply reduces delay while preserving strong noise margins. Across a range of tube diameters, this modified 10T design consistently shows shorter read and write times and a lower power–delay product than the other SRAM options, despite having more devices per cell.

What This Means for Future Devices

For non-specialists, the takeaway is that the internal “plumbing” of future memory chips—down to the thickness of each carbon tube and the choice of insulating films—can be tuned like knobs on a mixing board to balance speed, energy use, and reliability. The study demonstrates that carefully chosen nanotube diameters and advanced insulating materials, combined with an improved 10-transistor cell layout, can deliver SRAM that switches in picoseconds while maintaining low energy per operation and strong resistance to electrical noise. Such CNTFET-based SRAM cells could become key building blocks for next-generation low-power electronics, from always-on health monitors to AI accelerators that need fast, efficient on-chip memory.

Citation: Fuad, M.H., Nayan, M. Impact of material and structural parameters on the performance of advanced low-power CNTFET-based SRAM designs. Sci Rep 16, 11745 (2026). https://doi.org/10.1038/s41598-026-47254-7

Keywords: carbon nanotube transistors, low power memory, SRAM design, nanoelectronics, advanced transistor technologies