Interference-aware frequency-agile onboard processor using fine-grained multilevel analysis–synthesis filter-bank channelization

Sharper Ears for Busy Space Radios

Modern satellites and deep-space probes must listen to dozens or even hundreds of radio conversations at once, all squeezed into limited spectrum. This paper presents a new way for an onboard computer to untangle those overlapping signals into clean, separate channels using less hardware and power than many existing designs. The work is aimed at making future space missions more flexible, more interference‑resistant, and better able to adapt to crowded radio bands.

Why Spacecraft Need Smarter Listening

As more satellites share the sky, their radio links must pack many digital data streams into tightly spaced frequency slices. An onboard processor has to split a wide incoming band into uniform “slots,” keep neighboring channels from bleeding into one another, and then put selected channels back together with minimal distortion. Conventional techniques either rely on very large fast Fourier transforms, which can be memory‑hungry, or on banks of many separate filters, which consume hardware and power. Wavelet‑based methods, while mathematically elegant, often let neighboring channels overlap too much in frequency, which is bad news for recovering clean data bits.

A Single Filter Doing Many Jobs

The authors reformulate an existing mathematical tool, the maximal overlap wavelet packet transform, into a communication‑oriented channelizer. Instead of designing a different filter for every channel, they start from a single carefully crafted digital low‑pass filter and automatically generate all of the analysis and reconstruction filters by stretching and combining it in a multilevel tree. Because the transform is “non‑decimated,” it never throws away time samples as classic wavelets do, so the timing needed to decode symbols is preserved. This unified analysis–synthesis structure produces evenly spaced channels, each with the same delay and predictable behavior, while keeping memory and arithmetic demands low through heavy reuse of the same hardware blocks.

Balancing Signal Purity and Hardware Cost

Designing that lone prototype filter is the heart of the method. The team uses a multi‑objective optimization that weighs three concerns: how sharply each channel turns off at its edges (transition‑band energy), how little energy leaks into forbidden frequencies (stop‑band energy), and how long the filter is, which is a stand‑in for hardware cost. They add a practical communication constraint by simulating quadrature phase‑shift keying (QPSK) signals and rejecting any design that produces more than 10% error vector magnitude, a standard measure of distortion. By sweeping through candidate designs, they find an order‑105 equiripple filter that offers a good compromise: very clean separation between channels while keeping the arithmetic and memory needs within reach of real onboard electronics.

Putting the Design Through Its Paces

To test the idea, the authors simulate a demanding scenario: 64 QPSK carriers, each 10 kHz wide and packed on a uniform grid, forming a dense wideband signal. Their multilevel filter tree splits the band into 64 equal slices, then selectively recombines only one slice at a time to cancel out subtle phase twists introduced by block‑based FFT processing. Across all channels, the average isolation from neighboring channels exceeds 98 dB, with the worst case still close to 80 dB—far beyond what is typically needed for reliable QPSK links. The method scales naturally to coarser views (16 or 32 channels) by aggregating adjacent slices, which actually improves isolation further, and floating‑point tests up to 2048 channels show no numerical instability in the architecture itself.

From Equations to Space Hardware

The team then maps their design onto a mid‑range Xilinx Kintex‑7 FPGA, a popular class of reconfigurable space‑grade hardware. By processing data in blocks, time‑multiplexing a single FFT, a single inverse FFT, and one complex multiplier across all channels, they keep the number of digital signal processing blocks and memory blocks modest while sustaining a 160 MHz internal clock. Fixed‑point simulations with realistic word lengths still maintain worst‑case isolation above 60 dB and QPSK distortion under about 12%, confirming that the scheme survives the rounding errors inevitable in real hardware. The overall computational effort grows only logarithmically with block size and does not require duplicating filters per channel, making the design attractive for power‑ and area‑constrained onboard processors.

What This Means for Future Missions

In everyday terms, the paper shows how a spacecraft can use one very smart, reusable filter to sort a crowded radio band into many clean, adjustable lanes without carrying a rack full of specialized circuits. The result is a spectrally sharp, interference‑aware channelizer that can flex between fine and coarse resolution, preserve data integrity for standard digital modulations, and fit within realistic FPGA resources and power budgets. This unified framework lays a foundation for future satellite payloads that need to reconfigure their links on the fly, share spectrum more gracefully, and support more users without sacrificing signal quality.

Citation: Sarkar, S., Das, A., Mishra, D. et al. Interference-aware frequency-agile onboard processor using fine-grained multilevel analysis–synthesis filter-bank channelization. Sci Rep 16, 12772 (2026). https://doi.org/10.1038/s41598-026-43081-y

Keywords: satellite communications, digital signal processing, filter banks, onboard processors, multicarrier modulation